An ECO algorithm for resolving OPC and coupling capacitance violations

Hua Xiang; Li Da Huang; Kai Yuan Chao; Martin D. F. Wong

doi:10.1109/ICASIC.2005.1611444

An ECO algorithm for resolving OPC and coupling capacitance violations

Hua Xiang, Li Da Huang, Kai Yuan Chao, Martin D. F. Wong

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Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

3 Citations (Scopus)

Abstract

In the deep submicron manufacturing (DSM) era, lithography/yield and noise are critical issues to be considered. Optical proximity correction (OPC) is becoming a key compensate technique for the light diffraction effect in lithography. Both OPC effect and the capacitive coupling on some wire segments can only be analyzed post routing in late design stage or post-silicon stepping design change. ECO (engineering change orders) is used in late design stage to fix violations that exceed the given OPC and coupling capacitance thresholds derived from analysis. These violations must be corrected in order to guarantee performance and yield. In this paper, we propose the first ECO routing algorithm which eliminates both OPC and coupling capacitance violations for wires. At the same time, the ECO routing obeys the given constraints so as to keep the new routing solution close to the existing one to preserve design timing and layout convergence

Original language	English
Title of host publication	2005 6th International Conference on ASIC Proceedings, ASICON 2005
Editors	Ting Ao Tang, Yumei Huang
Place of Publication	China
Publisher	IEEE
Pages	784-787
Number of pages	4
Volume	2
DOIs	https://doi.org/10.1109/ICASIC.2005.1611444
Publication status	Published - Oct 2005
Event	2005 6th International Conference on ASIC, ASICON 2005 - Shanghai, China Duration: 24 Oct 2005 → 27 Oct 2005 https://ieeexplore.ieee.org/xpl/conhome/10726/proceeding (Link to conference proceedings)

Publication series

Name	International Conference on ASIC Proceeding
ISSN (Print)	2162-7541
ISSN (Electronic)	2162-755X

Conference

Conference	2005 6th International Conference on ASIC, ASICON 2005
Country/Territory	China
City	Shanghai
Period	24/10/05 → 27/10/05
Internet address	https://ieeexplore.ieee.org/xpl/conhome/10726/proceeding (Link to conference proceedings)

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10.1109/ICASIC.2005.1611444

Cite this

@inproceedings{19e9e4ecd52f40099db2eb9f3466d49e,

title = "An ECO algorithm for resolving OPC and coupling capacitance violations",

abstract = "In the deep submicron manufacturing (DSM) era, lithography/yield and noise are critical issues to be considered. Optical proximity correction (OPC) is becoming a key compensate technique for the light diffraction effect in lithography. Both OPC effect and the capacitive coupling on some wire segments can only be analyzed post routing in late design stage or post-silicon stepping design change. ECO (engineering change orders) is used in late design stage to fix violations that exceed the given OPC and coupling capacitance thresholds derived from analysis. These violations must be corrected in order to guarantee performance and yield. In this paper, we propose the first ECO routing algorithm which eliminates both OPC and coupling capacitance violations for wires. At the same time, the ECO routing obeys the given constraints so as to keep the new routing solution close to the existing one to preserve design timing and layout convergence",

author = "Hua Xiang and Huang, {Li Da} and Chao, {Kai Yuan} and Wong, {Martin D. F.}",

note = "Funding information: This work was partially supported by the National Science Foundation under grant CCR-0306244. Publisher copyright: {\textcopyright} 2005 IEEE; 2005 6th International Conference on ASIC, ASICON 2005 ; Conference date: 24-10-2005 Through 27-10-2005",

year = "2005",

month = oct,

doi = "10.1109/ICASIC.2005.1611444",

language = "English",

volume = "2",

series = "International Conference on ASIC Proceeding",

publisher = "IEEE",

pages = "784--787",

editor = "Tang, {Ting Ao} and Yumei Huang",

booktitle = "2005 6th International Conference on ASIC Proceedings, ASICON 2005",

address = "United States",

url = "https://ieeexplore.ieee.org/xpl/conhome/10726/proceeding",

}

Xiang, H, Huang, LD, Chao, KY & Wong, MDF 2005, An ECO algorithm for resolving OPC and coupling capacitance violations. in TA Tang & Y Huang (eds), 2005 6th International Conference on ASIC Proceedings, ASICON 2005. vol. 2, International Conference on ASIC Proceeding, IEEE, China, pp. 784-787, 2005 6th International Conference on ASIC, ASICON 2005, Shanghai, China, 24/10/05. https://doi.org/10.1109/ICASIC.2005.1611444

An ECO algorithm for resolving OPC and coupling capacitance violations. / Xiang, Hua; Huang, Li Da; Chao, Kai Yuan et al.
2005 6th International Conference on ASIC Proceedings, ASICON 2005. ed. / Ting Ao Tang; Yumei Huang. Vol. 2 China: IEEE, 2005. p. 784-787 (International Conference on ASIC Proceeding).

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

TY - GEN

T1 - An ECO algorithm for resolving OPC and coupling capacitance violations

AU - Xiang, Hua

AU - Huang, Li Da

AU - Chao, Kai Yuan

AU - Wong, Martin D. F.

PY - 2005/10

Y1 - 2005/10

N2 - In the deep submicron manufacturing (DSM) era, lithography/yield and noise are critical issues to be considered. Optical proximity correction (OPC) is becoming a key compensate technique for the light diffraction effect in lithography. Both OPC effect and the capacitive coupling on some wire segments can only be analyzed post routing in late design stage or post-silicon stepping design change. ECO (engineering change orders) is used in late design stage to fix violations that exceed the given OPC and coupling capacitance thresholds derived from analysis. These violations must be corrected in order to guarantee performance and yield. In this paper, we propose the first ECO routing algorithm which eliminates both OPC and coupling capacitance violations for wires. At the same time, the ECO routing obeys the given constraints so as to keep the new routing solution close to the existing one to preserve design timing and layout convergence

AB - In the deep submicron manufacturing (DSM) era, lithography/yield and noise are critical issues to be considered. Optical proximity correction (OPC) is becoming a key compensate technique for the light diffraction effect in lithography. Both OPC effect and the capacitive coupling on some wire segments can only be analyzed post routing in late design stage or post-silicon stepping design change. ECO (engineering change orders) is used in late design stage to fix violations that exceed the given OPC and coupling capacitance thresholds derived from analysis. These violations must be corrected in order to guarantee performance and yield. In this paper, we propose the first ECO routing algorithm which eliminates both OPC and coupling capacitance violations for wires. At the same time, the ECO routing obeys the given constraints so as to keep the new routing solution close to the existing one to preserve design timing and layout convergence

U2 - 10.1109/ICASIC.2005.1611444

DO - 10.1109/ICASIC.2005.1611444

M3 - Conference proceeding

VL - 2

T3 - International Conference on ASIC Proceeding

SP - 784

EP - 787

BT - 2005 6th International Conference on ASIC Proceedings, ASICON 2005

A2 - Tang, Ting Ao

A2 - Huang, Yumei

PB - IEEE

CY - China

T2 - 2005 6th International Conference on ASIC, ASICON 2005

Y2 - 24 October 2005 through 27 October 2005

ER -

An ECO algorithm for resolving OPC and coupling capacitance violations

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