An algorithm for hierarchical floorplan design

D.F. Wong; Khe-Sing The

doi:10.1109/ICCAD.1989.76996

An algorithm for hierarchical floorplan design

D.F. Wong, Khe-Sing The

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Research output: Chapter in book/report/conference proceeding › Conference proceeding

9 Citations (Scopus)

Abstract

A floorplan design algorithm is presented which is based on the following: (1) a new representation of order-5 hierarchical floorplan by normalized 2-5 Polish expressions; (2) a novel neighborhood structure defined by a set of four moves that bring a solution to its neighboring solutions; (3) an efficient floorplan area optimization algorithm for general hierarchical floorplans that makes the cost function evaluations possible; and (4) the search technique of simulated annealing. The algorithm generates nonslicing floorplans. It is a natural but nontrivial extension of the algorithm of D.F. Wong and C.L. Liu (Proc. 23rd ACM/IEEE Design Automation Conf., p.101-7, 1986). The present algorithm is compared with Wong and Liu's, and improvement was obtained in the test samples.

Original language	English
Title of host publication	1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers
Publisher	IEEE
Pages	484-487
Number of pages	4
ISBN (Print)	0818619864
DOIs	https://doi.org/10.1109/ICCAD.1989.76996
Publication status	Published - 9 Nov 1989
Event	1989 IEEE International Conference on Computer-Aided Design, ICCAD 1989 - Santa Clara, United States Duration: 5 Nov 1989 → 9 Nov 1989 https://ieeexplore.ieee.org/xpl/conhome/263/proceeding

Publication series

Name	IEEE International Conference on Computer-Aided Design

Conference

Conference	1989 IEEE International Conference on Computer-Aided Design, ICCAD 1989
Country/Territory	United States
City	Santa Clara
Period	5/11/89 → 9/11/89
Internet address	https://ieeexplore.ieee.org/xpl/conhome/263/proceeding

User-Defined Keywords

Algorithm design and analysis
Design optimization
Cost function
Simulated annealing
Computer simulation
Circuit testing
Very large scale integration
Integrated circuit interconnections
Wire
Area measurement

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10.1109/ICCAD.1989.76996

Cite this

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title = "An algorithm for hierarchical floorplan design",

abstract = "A floorplan design algorithm is presented which is based on the following: (1) a new representation of order-5 hierarchical floorplan by normalized 2-5 Polish expressions; (2) a novel neighborhood structure defined by a set of four moves that bring a solution to its neighboring solutions; (3) an efficient floorplan area optimization algorithm for general hierarchical floorplans that makes the cost function evaluations possible; and (4) the search technique of simulated annealing. The algorithm generates nonslicing floorplans. It is a natural but nontrivial extension of the algorithm of D.F. Wong and C.L. Liu (Proc. 23rd ACM/IEEE Design Automation Conf., p.101-7, 1986). The present algorithm is compared with Wong and Liu's, and improvement was obtained in the test samples.",

keywords = "Algorithm design and analysis, Design optimization, Cost function, Simulated annealing, Computer simulation, Circuit testing, Very large scale integration, Integrated circuit interconnections, Wire, Area measurement",

author = "D.F. Wong and Khe-Sing The",

note = "This work was partially supported by the Texas Advanced Research Program under grant 4096, by the National Science Foundation under grant MIP-8909586, and by an IBM Faculty Development Award.; 1989 IEEE International Conference on Computer-Aided Design, ICCAD 1989 ; Conference date: 05-11-1989 Through 09-11-1989",

year = "1989",

month = nov,

day = "9",

doi = "10.1109/ICCAD.1989.76996",

language = "English",

isbn = "0818619864",

series = "IEEE International Conference on Computer-Aided Design",

publisher = "IEEE",

pages = "484--487",

booktitle = "1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers",

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}

Wong, DF & The, K-S 1989, An algorithm for hierarchical floorplan design. in 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers. IEEE International Conference on Computer-Aided Design, IEEE, pp. 484-487, 1989 IEEE International Conference on Computer-Aided Design, ICCAD 1989, Santa Clara, California, United States, 5/11/89. https://doi.org/10.1109/ICCAD.1989.76996

TY - GEN

T1 - An algorithm for hierarchical floorplan design

AU - Wong, D.F.

AU - The, Khe-Sing

N1 - This work was partially supported by the Texas Advanced Research Program under grant 4096, by the National Science Foundation under grant MIP-8909586, and by an IBM Faculty Development Award.

PY - 1989/11/9

Y1 - 1989/11/9

N2 - A floorplan design algorithm is presented which is based on the following: (1) a new representation of order-5 hierarchical floorplan by normalized 2-5 Polish expressions; (2) a novel neighborhood structure defined by a set of four moves that bring a solution to its neighboring solutions; (3) an efficient floorplan area optimization algorithm for general hierarchical floorplans that makes the cost function evaluations possible; and (4) the search technique of simulated annealing. The algorithm generates nonslicing floorplans. It is a natural but nontrivial extension of the algorithm of D.F. Wong and C.L. Liu (Proc. 23rd ACM/IEEE Design Automation Conf., p.101-7, 1986). The present algorithm is compared with Wong and Liu's, and improvement was obtained in the test samples.

AB - A floorplan design algorithm is presented which is based on the following: (1) a new representation of order-5 hierarchical floorplan by normalized 2-5 Polish expressions; (2) a novel neighborhood structure defined by a set of four moves that bring a solution to its neighboring solutions; (3) an efficient floorplan area optimization algorithm for general hierarchical floorplans that makes the cost function evaluations possible; and (4) the search technique of simulated annealing. The algorithm generates nonslicing floorplans. It is a natural but nontrivial extension of the algorithm of D.F. Wong and C.L. Liu (Proc. 23rd ACM/IEEE Design Automation Conf., p.101-7, 1986). The present algorithm is compared with Wong and Liu's, and improvement was obtained in the test samples.

KW - Algorithm design and analysis

KW - Design optimization

KW - Cost function

KW - Simulated annealing

KW - Computer simulation

KW - Circuit testing

KW - Very large scale integration

KW - Integrated circuit interconnections

KW - Wire

KW - Area measurement

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U2 - 10.1109/ICCAD.1989.76996

DO - 10.1109/ICCAD.1989.76996

M3 - Conference proceeding

SN - 0818619864

T3 - IEEE International Conference on Computer-Aided Design

SP - 484

EP - 487

BT - 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers

PB - IEEE

T2 - 1989 IEEE International Conference on Computer-Aided Design, ICCAD 1989

Y2 - 5 November 1989 through 9 November 1989

ER -

An algorithm for hierarchical floorplan design

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