An algorithm for hierarchical floorplan design

D.F. Wong, Khe-Sing The

Research output: Chapter in book/report/conference proceedingConference proceeding

8 Citations (Scopus)

Abstract

A floorplan design algorithm is presented which is based on the following: (1) a new representation of order-5 hierarchical floorplan by normalized 2-5 Polish expressions; (2) a novel neighborhood structure defined by a set of four moves that bring a solution to its neighboring solutions; (3) an efficient floorplan area optimization algorithm for general hierarchical floorplans that makes the cost function evaluations possible; and (4) the search technique of simulated annealing. The algorithm generates nonslicing floorplans. It is a natural but nontrivial extension of the algorithm of D.F. Wong and C.L. Liu (Proc. 23rd ACM/IEEE Design Automation Conf., p.101-7, 1986). The present algorithm is compared with Wong and Liu's, and improvement was obtained in the test samples.
Original languageEnglish
Title of host publication1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers
PublisherIEEE
Pages484-487
Number of pages4
ISBN (Print)0818619864
DOIs
Publication statusPublished - 9 Nov 1989
Event1989 IEEE International Conference on Computer-Aided Design, ICCAD 1989 - Santa Clara, United States
Duration: 5 Nov 19899 Nov 1989
https://ieeexplore.ieee.org/xpl/conhome/263/proceeding

Publication series

NameIEEE International Conference on Computer-Aided Design

Conference

Conference1989 IEEE International Conference on Computer-Aided Design, ICCAD 1989
Country/TerritoryUnited States
CitySanta Clara
Period5/11/899/11/89
Internet address

User-Defined Keywords

  • Algorithm design and analysis
  • Design optimization
  • Cost function
  • Simulated annealing
  • Computer simulation
  • Circuit testing
  • Very large scale integration
  • Integrated circuit interconnections
  • Wire
  • Area measurement

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