Advances in transistor timing, simulation, and optimization

Jacob Avidan; Abe Elfadel; D. F. Wong

Advances in transistor timing, simulation, and optimization

Jacob Avidan, Abe Elfadel, D. F. Wong

Office of the Provost

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

Abstract

In circuit design, a transistor-level view has become a paramount importance for successful designs, especially in the very demanding context of high performance microprocessor design in the deep-submicron regime. In this paper this transistor level view is considered. The VLSI custom design problem is approach from the three perspectives of transistor-level static timing analysis, fast transistor-level simulation and transistor-level optimization process.

Original language	English
Title of host publication	Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, ICCAD 1999
Publisher	IEEE
Pages	611
Number of pages	1
ISBN (Print)	9780780358324
Publication status	Published - Nov 1999
Event	1999 IEEE International Conference on Computer-Aided Design, ICCAD 1999 - San Jose, United States Duration: 7 Nov 1999 → 11 Nov 1999 https://ieeexplore.ieee.org/xpl/conhome/6570/proceeding (Conference proceedings) https://dl.acm.org/doi/proceedings/10.5555/339492

Publication series

Name	IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers
Publisher	IEEE
ISSN (Print)	1092-3152

Conference

Conference	1999 IEEE International Conference on Computer-Aided Design, ICCAD 1999
Country/Territory	United States
City	San Jose
Period	7/11/99 → 11/11/99
Internet address	https://ieeexplore.ieee.org/xpl/conhome/6570/proceeding (Conference proceedings) https://dl.acm.org/doi/proceedings/10.5555/339492

Cite this

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title = "Advances in transistor timing, simulation, and optimization",

abstract = "In circuit design, a transistor-level view has become a paramount importance for successful designs, especially in the very demanding context of high performance microprocessor design in the deep-submicron regime. In this paper this transistor level view is considered. The VLSI custom design problem is approach from the three perspectives of transistor-level static timing analysis, fast transistor-level simulation and transistor-level optimization process.",

author = "Jacob Avidan and Abe Elfadel and Wong, {D. F.}",

year = "1999",

month = nov,

language = "English",

isbn = "9780780358324",

series = "IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers",

publisher = "IEEE",

pages = "611",

booktitle = "Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, ICCAD 1999",

address = "United States",

note = "1999 IEEE International Conference on Computer-Aided Design, ICCAD 1999 ; Conference date: 07-11-1999 Through 11-11-1999",

url = "https://ieeexplore.ieee.org/xpl/conhome/6570/proceeding, https://dl.acm.org/doi/proceedings/10.5555/339492",

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Avidan, J, Elfadel, A & Wong, DF 1999, Advances in transistor timing, simulation, and optimization. in Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, ICCAD 1999 . IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers, IEEE, pp. 611, 1999 IEEE International Conference on Computer-Aided Design, ICCAD 1999, San Jose, California, United States, 7/11/99.

Advances in transistor timing, simulation, and optimization. / Avidan, Jacob; Elfadel, Abe; Wong, D. F.
Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, ICCAD 1999 . IEEE, 1999. p. 611 (IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers).

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

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AU - Wong, D. F.

PY - 1999/11

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N2 - In circuit design, a transistor-level view has become a paramount importance for successful designs, especially in the very demanding context of high performance microprocessor design in the deep-submicron regime. In this paper this transistor level view is considered. The VLSI custom design problem is approach from the three perspectives of transistor-level static timing analysis, fast transistor-level simulation and transistor-level optimization process.

AB - In circuit design, a transistor-level view has become a paramount importance for successful designs, especially in the very demanding context of high performance microprocessor design in the deep-submicron regime. In this paper this transistor level view is considered. The VLSI custom design problem is approach from the three perspectives of transistor-level static timing analysis, fast transistor-level simulation and transistor-level optimization process.

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BT - Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design, ICCAD 1999

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ER -

Advances in transistor timing, simulation, and optimization

Abstract

Publication series

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