Abstract
This paper presents a generic approach of exploiting GPU parallelism to speed up the essential computations in VLSI nonlinear analytical placement. We consider the computation of wirelength and density which are widely used as cost and constraint in nonlinear analytical placement. For wirelength gradient computing, we utilize the sparse characteristic of circuit graph to transform the compute-intensive portions into sparse matrix multiplications, which effectively optimizes the memory access pattern and mitigates the imbalance workload. For density, we introduce a computation flattening technique to achieve load balancing among threads and a High-Precision representation is integrated into our approach to guarantee the reproducibility. We have evaluated our method on a set of contest benchmarks from industry. The experimental results demonstrate our GPU method achieves a better performance over both the CPU methods and the straightforward GPU implementation.
Original language | English |
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Title of host publication | 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE) |
Publisher | IEEE |
Pages | 1345-1350 |
Number of pages | 6 |
ISBN (Electronic) | 9783981926309, 9783981926316 (USB) |
DOIs | |
Publication status | Published - Mar 2018 |
Event | 2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018 - Dresden, Germany Duration: 19 Mar 2018 → 23 Mar 2018 https://ieeexplore.ieee.org/xpl/conhome/8337149/proceeding (Link to conference proceedings) |
Publication series
Name | Proceedings of Design, Automation & Test in Europe Conference & Exhibition |
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Conference
Conference | 2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018 |
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Country/Territory | Germany |
City | Dresden |
Period | 19/03/18 → 23/03/18 |
Internet address |
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