A routing approach to reduce glitches in low power FPGAS

Quang Dinh; Deming Chen; Martin D. F. Wong

doi:10.1145/1514932.1514956

A routing approach to reduce glitches in low power FPGAS

Quang Dinh, Deming Chen, Martin D. F. Wong

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Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

8 Citations (Scopus)

Abstract

Glitches (spurious transitions) are common in electronic circuits. In this paper we present a novel approach to reduce dynamic power in FPGAs by reducing glitches during the routing step. This approach involves finding alternative routes for early-arriving signals, so that signal arrival times at LUTs are aligned and no glitches are generated. This approach does not require additional circuitry to balance signals as done in previous work, but uses the available programmable routing resources instead. We develop an efficient algorithm to find routes with target delays. Based on this algorithm, we then build a glitch-aware router, named GlitchReroute, aiming at reducing dynamic power. To the best of our knowledge, this is the first glitch-aware routing algorithm for FPGAs. Experiments show that an average of 23% reduction in glitch power is achieved, which translates into a 9.8% reduction in dynamic power, compared to the glitch-unaware VPR router.

Original language	English
Title of host publication	ISPD '09
Subtitle of host publication	Proceedings of the 2009 International Symposium on Physical Design, ISPD'09
Publisher	Association for Computing Machinery (ACM)
Pages	99-105
Number of pages	7
ISBN (Print)	9781605584492
DOIs	https://doi.org/10.1145/1514932.1514956
Publication status	Published - 29 Mar 2009
Event	18th International Symposium on Physical Design, ISPD 2009 - San Diego, United States Duration: 29 Mar 2009 → 1 Apr 2009 https://dl.acm.org/doi/proceedings/10.1145/1514932 (Conference proceedings)

Publication series

Name	Proceedings of the International Symposium on Physical Design, ISPD

Symposium

Symposium	18th International Symposium on Physical Design, ISPD 2009
Country/Territory	United States
City	San Diego
Period	29/03/09 → 1/04/09
Internet address	https://dl.acm.org/doi/proceedings/10.1145/1514932 (Conference proceedings)

User-Defined Keywords

FPGAs
Low Power
Glitch Reduction
Path Balancing
Routing.

Access to Document

10.1145/1514932.1514956

Cite this

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title = "A routing approach to reduce glitches in low power FPGAS",

abstract = "Glitches (spurious transitions) are common in electronic circuits. In this paper we present a novel approach to reduce dynamic power in FPGAs by reducing glitches during the routing step. This approach involves finding alternative routes for early-arriving signals, so that signal arrival times at LUTs are aligned and no glitches are generated. This approach does not require additional circuitry to balance signals as done in previous work, but uses the available programmable routing resources instead. We develop an efficient algorithm to find routes with target delays. Based on this algorithm, we then build a glitch-aware router, named GlitchReroute, aiming at reducing dynamic power. To the best of our knowledge, this is the first glitch-aware routing algorithm for FPGAs. Experiments show that an average of 23% reduction in glitch power is achieved, which translates into a 9.8% reduction in dynamic power, compared to the glitch-unaware VPR router.",

keywords = "FPGAs, Low Power, Glitch Reduction, Path Balancing, Routing.",

author = "Quang Dinh and Deming Chen and Wong, {Martin D. F.}",

note = "This work is partially supported by a grant from Altera Corp, by NSF grant CCF-0746608, and by NSF grant CCF-0701821. We wish also to thank Chen Dong, ECE, University of Illinois at Urbana-Champaign for his support on fpgaEVA-LP2.; 18th International Symposium on Physical Design, ISPD 2009 ; Conference date: 29-03-2009 Through 01-04-2009",

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doi = "10.1145/1514932.1514956",

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Dinh, Q, Chen, D & Wong, MDF 2009, A routing approach to reduce glitches in low power FPGAS. in ISPD '09: Proceedings of the 2009 International Symposium on Physical Design, ISPD'09. Proceedings of the International Symposium on Physical Design, ISPD, Association for Computing Machinery (ACM), pp. 99-105, 18th International Symposium on Physical Design, ISPD 2009, San Diego, California, United States, 29/03/09. https://doi.org/10.1145/1514932.1514956

A routing approach to reduce glitches in low power FPGAS. / Dinh, Quang; Chen, Deming; Wong, Martin D. F.
ISPD '09: Proceedings of the 2009 International Symposium on Physical Design, ISPD'09. Association for Computing Machinery (ACM), 2009. p. 99-105 (Proceedings of the International Symposium on Physical Design, ISPD).

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

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AU - Dinh, Quang

AU - Chen, Deming

AU - Wong, Martin D. F.

N1 - This work is partially supported by a grant from Altera Corp, by NSF grant CCF-0746608, and by NSF grant CCF-0701821. We wish also to thank Chen Dong, ECE, University of Illinois at Urbana-Champaign for his support on fpgaEVA-LP2.

PY - 2009/3/29

Y1 - 2009/3/29

N2 - Glitches (spurious transitions) are common in electronic circuits. In this paper we present a novel approach to reduce dynamic power in FPGAs by reducing glitches during the routing step. This approach involves finding alternative routes for early-arriving signals, so that signal arrival times at LUTs are aligned and no glitches are generated. This approach does not require additional circuitry to balance signals as done in previous work, but uses the available programmable routing resources instead. We develop an efficient algorithm to find routes with target delays. Based on this algorithm, we then build a glitch-aware router, named GlitchReroute, aiming at reducing dynamic power. To the best of our knowledge, this is the first glitch-aware routing algorithm for FPGAs. Experiments show that an average of 23% reduction in glitch power is achieved, which translates into a 9.8% reduction in dynamic power, compared to the glitch-unaware VPR router.

AB - Glitches (spurious transitions) are common in electronic circuits. In this paper we present a novel approach to reduce dynamic power in FPGAs by reducing glitches during the routing step. This approach involves finding alternative routes for early-arriving signals, so that signal arrival times at LUTs are aligned and no glitches are generated. This approach does not require additional circuitry to balance signals as done in previous work, but uses the available programmable routing resources instead. We develop an efficient algorithm to find routes with target delays. Based on this algorithm, we then build a glitch-aware router, named GlitchReroute, aiming at reducing dynamic power. To the best of our knowledge, this is the first glitch-aware routing algorithm for FPGAs. Experiments show that an average of 23% reduction in glitch power is achieved, which translates into a 9.8% reduction in dynamic power, compared to the glitch-unaware VPR router.

KW - FPGAs

KW - Low Power

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ER -

A routing approach to reduce glitches in low power FPGAS

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