A Routing Approach to Reduce Glitches in Low Power FPGAs

Quang Dinh, Deming Chen, Martin D. F. Wong

Research output: Contribution to journalJournal articlepeer-review

14 Citations (Scopus)


This paper presents a novel approach to reduce dynamic power in field-programmable gate arrays (FPGAs) by reducing glitches during routing. It finds alternative routes for early-arriving signals so that signal arrival times at look-up tables are aligned. We developed an efficient algorithm to find routes with target delays and then built a glitch-aware router aiming at reducing dynamic power. To the best of our knowledge, this is the first glitch-aware routing algorithm for FPGAs. Experiments show that an average of 27% reduction in glitch power is achieved, which translates into an 11% reduction in dynamic power, compared to the glitch-unaware versatile place and route's router.

Original languageEnglish
Pages (from-to)235-240
Number of pages6
JournalIEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Issue number2
Early online date22 Jan 2010
Publication statusPublished - Feb 2010

Scopus Subject Areas

  • Software
  • Computer Graphics and Computer-Aided Design
  • Electrical and Electronic Engineering

User-Defined Keywords

  • FPGA
  • Glitch reduction
  • Low power
  • Path balancing
  • Routing


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