A parallel architecture using discrete wavelet transform for fast ICA implementation

Rong Bo Huang; Yiu Ming Cheung; Shi Ming Zhu

doi:10.1109/ICNNSP.2003.1281124

A parallel architecture using discrete wavelet transform for fast ICA implementation

Rong Bo Huang^*, Yiu Ming Cheung, Shi Ming Zhu

^*Corresponding author for this work

Department of Computer Science

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

2 Citations (Scopus)

Abstract

This paper utilizes a discrete wavelet transform to present a parallel architecture for independent component analysis (ICA), which is a hybrid system consisting of two sub-ICA processes. One process takes the high-frequency wavelet part of observations as its input, meanwhile the other process takes the low-frequency part. Their results are then merged to generate the final ICA results. Compared to the existing ICA algorithms, the proposed approach utilizes the full observation information, but the effective input length of the two parallel processes is halved. It therefore generally provides a new way for fast ICA implementation. In this paper, the experimental result has shown its success in extracting the independent components from a mixture.

Original language	English
Title of host publication	Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03
Pages	1358-1361
Number of pages	4
DOIs	https://doi.org/10.1109/ICNNSP.2003.1281124
Publication status	Published - 2003
Event	2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03 - Nanjing, China Duration: 14 Dec 2003 → 17 Dec 2003

Publication series

Name	Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03
Volume	2

Conference

Conference	2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03
Country/Territory	China
City	Nanjing
Period	14/12/03 → 17/12/03

Scopus Subject Areas

Signal Processing
Computer Networks and Communications

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10.1109/ICNNSP.2003.1281124

Cite this

Huang, R. B., Cheung, Y. M., & Zhu, S. M. (2003). A parallel architecture using discrete wavelet transform for fast ICA implementation. In Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03 (pp. 1358-1361). Article 1281124 (Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03; Vol. 2). https://doi.org/10.1109/ICNNSP.2003.1281124

@inproceedings{e426a90639e54de68e1ec83a2c8e7446,

title = "A parallel architecture using discrete wavelet transform for fast ICA implementation",

abstract = "This paper utilizes a discrete wavelet transform to present a parallel architecture for independent component analysis (ICA), which is a hybrid system consisting of two sub-ICA processes. One process takes the high-frequency wavelet part of observations as its input, meanwhile the other process takes the low-frequency part. Their results are then merged to generate the final ICA results. Compared to the existing ICA algorithms, the proposed approach utilizes the full observation information, but the effective input length of the two parallel processes is halved. It therefore generally provides a new way for fast ICA implementation. In this paper, the experimental result has shown its success in extracting the independent components from a mixture.",

author = "Huang, {Rong Bo} and Cheung, {Yiu Ming} and Zhu, {Shi Ming}",

note = "Copyright: Copyright 2011 Elsevier B.V., All rights reserved.; 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03 ; Conference date: 14-12-2003 Through 17-12-2003",

year = "2003",

doi = "10.1109/ICNNSP.2003.1281124",

language = "English",

isbn = "0780377028",

series = "Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03",

pages = "1358--1361",

booktitle = "Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03",

}

Huang, RB, Cheung, YM & Zhu, SM 2003, A parallel architecture using discrete wavelet transform for fast ICA implementation. in Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03., 1281124, Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03, vol. 2, pp. 1358-1361, 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03, Nanjing, China, 14/12/03. https://doi.org/10.1109/ICNNSP.2003.1281124

A parallel architecture using discrete wavelet transform for fast ICA implementation. / Huang, Rong Bo; Cheung, Yiu Ming; Zhu, Shi Ming.
Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03. 2003. p. 1358-1361 1281124 (Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03; Vol. 2).

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

TY - GEN

T1 - A parallel architecture using discrete wavelet transform for fast ICA implementation

AU - Huang, Rong Bo

AU - Cheung, Yiu Ming

AU - Zhu, Shi Ming

PY - 2003

Y1 - 2003

N2 - This paper utilizes a discrete wavelet transform to present a parallel architecture for independent component analysis (ICA), which is a hybrid system consisting of two sub-ICA processes. One process takes the high-frequency wavelet part of observations as its input, meanwhile the other process takes the low-frequency part. Their results are then merged to generate the final ICA results. Compared to the existing ICA algorithms, the proposed approach utilizes the full observation information, but the effective input length of the two parallel processes is halved. It therefore generally provides a new way for fast ICA implementation. In this paper, the experimental result has shown its success in extracting the independent components from a mixture.

AB - This paper utilizes a discrete wavelet transform to present a parallel architecture for independent component analysis (ICA), which is a hybrid system consisting of two sub-ICA processes. One process takes the high-frequency wavelet part of observations as its input, meanwhile the other process takes the low-frequency part. Their results are then merged to generate the final ICA results. Compared to the existing ICA algorithms, the proposed approach utilizes the full observation information, but the effective input length of the two parallel processes is halved. It therefore generally provides a new way for fast ICA implementation. In this paper, the experimental result has shown its success in extracting the independent components from a mixture.

UR - http://www.scopus.com/inward/record.url?scp=34047199741&partnerID=8YFLogxK

U2 - 10.1109/ICNNSP.2003.1281124

DO - 10.1109/ICNNSP.2003.1281124

M3 - Conference proceeding

AN - SCOPUS:34047199741

SN - 0780377028

SN - 9780780377028

T3 - Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03

SP - 1358

EP - 1361

BT - Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03

T2 - 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03

Y2 - 14 December 2003 through 17 December 2003

ER -

Huang RB, Cheung YM, Zhu SM. A parallel architecture using discrete wavelet transform for fast ICA implementation. In Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03. 2003. p. 1358-1361. 1281124. (Proceedings of 2003 International Conference on Neural Networks and Signal Processing, ICNNSP'03). doi: 10.1109/ICNNSP.2003.1281124

A parallel architecture using discrete wavelet transform for fast ICA implementation

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