A novel and efficient method for power pad placement optimization

Research output: Chapter in book/report/conference proceedingConference proceedingpeer-review

5 Citations (Scopus)

Abstract

In this paper, we propose a novel and efficient iterative method for pad placement optimization of power grid with flip chip technology. Power grid with optimized pad placement has less IR-drop values. We develop a new method to calculate new locations of all pads. Placing pads at the new locations reduces local IR-drop values. In order to reduce global IR-drop values, we develop a graph-based strategy to decide which pads are moved to the new locations. After each movement of the pads, a static IR-drop analysis is performed. We develop multigrid accelerated modified Simulated Annealing method (MG_SA) and compare it with the proposed method on a set of test cases. Experimental results show that the proposed method outperforms MG_SA with similar or less IR-drop values and much less runtime.
Original languageEnglish
Title of host publicationProceedings of the Fourteenth International Symposium on Quality Electronic Design ISQED 2013
EditorsMark Budnik, Keith Bowman
PublisherIEEE
Pages158-163
Number of pages6
ISBN (Electronic)9781467349536, 9781467349529
ISBN (Print)9781467349512
DOIs
Publication statusPublished - 4 Mar 2013
Event14th International Symposium on Quality Electronic Design, ISQED 2013 - Santa Clara, United States
Duration: 4 Mar 20136 Mar 2013
https://ieeexplore.ieee.org/xpl/conhome/6520923/proceeding (Conference proceedings)

Publication series

NameInternational Symposium on Quality Electronic Design (ISQED)
PublisherIEEE
ISSN (Print)1948-3287

Symposium

Symposium14th International Symposium on Quality Electronic Design, ISQED 2013
Country/TerritoryUnited States
CitySanta Clara
Period4/03/136/03/13
Internet address

User-Defined Keywords

  • power grid
  • pad placement
  • IR-drop
  • Runtime

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