Abstract
In this paper, we propose a novel and efficient iterative method for pad placement optimization of power grid with flip chip technology. Power grid with optimized pad placement has less IR-drop values. We develop a new method to calculate new locations of all pads. Placing pads at the new locations reduces local IR-drop values. In order to reduce global IR-drop values, we develop a graph-based strategy to decide which pads are moved to the new locations. After each movement of the pads, a static IR-drop analysis is performed. We develop multigrid accelerated modified Simulated Annealing method (MG_SA) and compare it with the proposed method on a set of test cases. Experimental results show that the proposed method outperforms MG_SA with similar or less IR-drop values and much less runtime.
Original language | English |
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Title of host publication | Proceedings of the Fourteenth International Symposium on Quality Electronic Design ISQED 2013 |
Editors | Mark Budnik, Keith Bowman |
Publisher | IEEE |
Pages | 158-163 |
Number of pages | 6 |
ISBN (Electronic) | 9781467349536, 9781467349529 |
ISBN (Print) | 9781467349512 |
DOIs | |
Publication status | Published - 4 Mar 2013 |
Event | 14th International Symposium on Quality Electronic Design, ISQED 2013 - Santa Clara, United States Duration: 4 Mar 2013 → 6 Mar 2013 https://ieeexplore.ieee.org/xpl/conhome/6520923/proceeding (Conference proceedings) |
Publication series
Name | International Symposium on Quality Electronic Design (ISQED) |
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Publisher | IEEE |
ISSN (Print) | 1948-3287 |
Symposium
Symposium | 14th International Symposium on Quality Electronic Design, ISQED 2013 |
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Country/Territory | United States |
City | Santa Clara |
Period | 4/03/13 → 6/03/13 |
Internet address |
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User-Defined Keywords
- power grid
- pad placement
- IR-drop
- Runtime