A New Algorithm for Floorplan Design

D. F. Wong; C. L. Liu

doi:10.1109/DAC.1986.1586075

A New Algorithm for Floorplan Design

D. F. Wong, C. L. Liu

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Research output: Chapter in book/report/conference proceeding › Conference proceeding

399 Citations (Scopus)

Abstract

We present in this paper a new algorithm for floorplan design using the method of simulated annealing. The major contributions of the paper are: 1. A new representation of floorplans (normalized Polish expressions) which enables us to carry out the neighborhood search effectively. 2. A simultaneous minimization of area and total interconnection length in the final solution. Experimental results indicate that the algorithm performs well in many test problems.

Original language	English
Title of host publication	23rd ACM/IEEE Design Automation Conference - Proceedings 1986
Publisher	IEEE
Pages	101-107
Number of pages	7
ISBN (Print)	0818607025, 9780818607028
DOIs	https://doi.org/10.1109/DAC.1986.1586075 https://doi.org/10.1145/318013.318030
Publication status	Published - 2 Jul 1986
Event	23rd ACM/IEEE Design Automation Conference, DAC 1986 - Las Vegas, NV, United States Duration: 29 Jun 1986 → 2 Jul 1986 https://ieeexplore.ieee.org/xpl/conhome/10572/proceeding https://dl.acm.org/doi/proceedings/10.5555/318013

Publication series

Name	ACM/IEEE Design Automation Conference - Proceedings
ISSN (Print)	0738-100X

Conference

Conference	23rd ACM/IEEE Design Automation Conference, DAC 1986
Country/Territory	United States
City	Las Vegas, NV
Period	29/06/86 → 2/07/86
Internet address	https://ieeexplore.ieee.org/xpl/conhome/10572/proceeding https://dl.acm.org/doi/proceedings/10.5555/318013

User-Defined Keywords

Algorithm design and analysis
Shape
Simulated annealing
Computer science
Design methodology
Computational modeling
Computer simulation
Minimization
Integrated circuit interconnections
Performance evaluation

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@inproceedings{03bb33964e894f13af93c8d7b5b5f671,

title = "A New Algorithm for Floorplan Design",

abstract = "We present in this paper a new algorithm for floorplan design using the method of simulated annealing. The major contributions of the paper are: 1. A new representation of floorplans (normalized Polish expressions) which enables us to carry out the neighborhood search effectively. 2. A simultaneous minimization of area and total interconnection length in the final solution. Experimental results indicate that the algorithm performs well in many test problems.",

keywords = "Algorithm design and analysis, Shape, Simulated annealing, Computer science, Design methodology, Computational modeling, Computer simulation, Minimization, Integrated circuit interconnections, Performance evaluation",

author = "Wong, {D. F.} and Liu, {C. L.}",

note = "This work was partially supported by the National Science Foundation under grant DCR 84-04239 and by a grant from the General Electric Company.; 23rd ACM/IEEE Design Automation Conference, DAC 1986 ; Conference date: 29-06-1986 Through 02-07-1986",

year = "1986",

month = jul,

day = "2",

doi = "10.1109/DAC.1986.1586075",

language = "English",

isbn = "0818607025",

series = "ACM/IEEE Design Automation Conference - Proceedings",

publisher = "IEEE",

pages = "101--107",

booktitle = "23rd ACM/IEEE Design Automation Conference - Proceedings 1986",

address = "United States",

url = "https://ieeexplore.ieee.org/xpl/conhome/10572/proceeding, https://dl.acm.org/doi/proceedings/10.5555/318013",

}

Wong, DF & Liu, CL 1986, A New Algorithm for Floorplan Design. in 23rd ACM/IEEE Design Automation Conference - Proceedings 1986. ACM/IEEE Design Automation Conference - Proceedings, IEEE, pp. 101-107, 23rd ACM/IEEE Design Automation Conference, DAC 1986, Las Vegas, NV, United States, 29/06/86. https://doi.org/10.1109/DAC.1986.1586075, https://doi.org/10.1145/318013.318030

TY - GEN

T1 - A New Algorithm for Floorplan Design

AU - Wong, D. F.

AU - Liu, C. L.

N1 - This work was partially supported by the National Science Foundation under grant DCR 84-04239 and by a grant from the General Electric Company.

PY - 1986/7/2

Y1 - 1986/7/2

N2 - We present in this paper a new algorithm for floorplan design using the method of simulated annealing. The major contributions of the paper are: 1. A new representation of floorplans (normalized Polish expressions) which enables us to carry out the neighborhood search effectively. 2. A simultaneous minimization of area and total interconnection length in the final solution. Experimental results indicate that the algorithm performs well in many test problems.

AB - We present in this paper a new algorithm for floorplan design using the method of simulated annealing. The major contributions of the paper are: 1. A new representation of floorplans (normalized Polish expressions) which enables us to carry out the neighborhood search effectively. 2. A simultaneous minimization of area and total interconnection length in the final solution. Experimental results indicate that the algorithm performs well in many test problems.

KW - Algorithm design and analysis

KW - Shape

KW - Simulated annealing

KW - Computer science

KW - Design methodology

KW - Computational modeling

KW - Computer simulation

KW - Minimization

KW - Integrated circuit interconnections

KW - Performance evaluation

UR - https://ieeexplore.ieee.org/document/1586075/

UR - https://dl.acm.org/doi/10.5555/318013.318030

U2 - 10.1109/DAC.1986.1586075

DO - 10.1109/DAC.1986.1586075

M3 - Conference proceeding

SN - 0818607025

SN - 9780818607028

T3 - ACM/IEEE Design Automation Conference - Proceedings

SP - 101

EP - 107

BT - 23rd ACM/IEEE Design Automation Conference - Proceedings 1986

PB - IEEE

T2 - 23rd ACM/IEEE Design Automation Conference, DAC 1986

Y2 - 29 June 1986 through 2 July 1986

ER -

A New Algorithm for Floorplan Design

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