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A More Precise Model of Noise Based PCMOS Errors

  • Arun Bhanu
  • , Mark S.K. Lau
  • , Keck Voon Ling
  • , Vincent J. Mooney
  • , Anshul Singh

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

14 Citations (Scopus)

Abstract

In this paper we present a new model for characterization of probabilistic gates. While still not mainstream, probabilistic CMOS has the potential to dramatically reduce energy consumption by trading off with error rates on individual bits, e.g., least significant bits of an adder. Our contribution helps account for the filtering effect seen in noise based PCMOS in a novel way. The characterization proposed here can enable accurate multi-bit models based on fast mathematical extrapolation instead of expensive and slow HSPICE simulations.

Original languageEnglish
Title of host publicationProceedings - 5th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2010
PublisherIEEE
Pages99-102
Number of pages4
ISBN (Electronic)9781424460267
ISBN (Print)9781424460250, 9780769539782
DOIs
Publication statusPublished - 13 Jan 2010
Event5th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2010 - Ho Chi Minh City, Viet Nam
Duration: 13 Jan 2010 → 15 Jan 2010
https://ieeexplore.ieee.org/xpl/conhome/5438527/proceeding (Conference Proceedings)

Publication series

NameProceedings - IEEE International Symposium on Electronic Design, Test and Applications, DELTA

Conference

Conference5th IEEE International Symposium on Electronic Design, Test and Applications, DELTA 2010
Country/TerritoryViet Nam
CityHo Chi Minh City
Period13/01/10 → 15/01/10
Internet address

UN SDGs

This output contributes to the following UN Sustainable Development Goals (SDGs)

  1. SDG 7 - Affordable and Clean Energy
    SDG 7 Affordable and Clean Energy

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