A Min-Cost Flow Based Detailed Router for FPGAs

Routing for FPGAs has been a very challenging problem due to the limitation of routing resources. Although the FPGA routing problem has been researched extensively, most algorithms route one net at a time, and it can cause the net-ordering problem.

In this paper, we present a detailed routing algorithm for FPGAs based on min-cost flow computations. Using the min-cost flow approach, our algorithm routes all the nets connected to a common logic module simultaneously. At each stage of the network flow computation, we guarantee optimal result in terms of routability and delay cost. For further improvement, we adopt an iterative refinement scheme based on the Lagrangian relaxation technique. The Lagrangian relaxation approach transforms the routing problem into a sequence of Lagrangian subproblems. At each iteration of the algorithm, Lagrangian subproblems are solved by our min-cost flow based routing algorithm. Any violation of congestion constraints is reflected in the value of corresponding Lagrangian multiplier. The Lagrangian multipliers are incorporated into the cost of each routing rosource node and guide the router.

Because our min-cost flow based algorithm minimizes cost function while it maximizes the flow, our algorithm finds congestion-free routing solutions with minimum total delay. Comparison with VPR router shows that our router uses less or equal number of routing tracks with smaller critical path delay as well as total routing delay.