A highly compressed timing macro-modeling algorithm for hierarchical and incremental timing analysis

Large-scale hierarchical and incremental timing analysis has driven the need for highly compressed timing macro-models. A small timing macro-model for accelerating hierarchical timing is desired because the size of incremental changes dramatically increases as the macro-models are widely used in the large design process. In fact, it takes days for an incremental timing analysis on millions of gates with thousands of incremental changes. To date, the timing macro-models generated by timing macro-modeling algorithms from all the previous works are not compact enough. In this work, we provide four essential techniques in our timing macro-modeling algorithm, which are able to generate highly compressed timing macro-models for hierarchical and incremental timing analysis. In addition, our timing macro-model maintain high accuracy and the efficiency in generating our macro-models. Our algorithm generates timing macro-models where the model sizes are 9% better in the number of nodes and 19% better in the number of edges than the original circuit. Our work outperforms the state of arts significantly in both model size and the runtime in macro-model usage.