Abstract
A new graph partitioning problem is introduced. It stems from a multiple-chip design style in which there is a chip library of chips containing predesigned circuit components (e.g., adders, multipliers, etc.) which are frequently used. Given an arbitrary circuit data flow graph, it is necessary to realize the circuit by appropriately choosing a set of chips from the chip library. In selecting chips from the chip library to realize a given circuit, both the number of chips used and the interconnection cost are to be minimized. The authors' new graph partitioning problem models this chip selection problem. An efficient solution to this problem is presented.
Original language | English |
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Title of host publication | 1993 IEEE International Symposium on Circuits and Systems (ISCAS) |
Publisher | IEEE |
Pages | 1778-1781 |
Number of pages | 4 |
ISBN (Print) | 0780312813 |
DOIs | |
Publication status | Published - 6 May 1993 |
Event | 1993 IEEE International Symposium on Circuits and Systems (ISCAS) - Chicago, United States Duration: 3 May 1993 → 6 May 1993 https://ieeexplore.ieee.org/xpl/conhome/1067/proceeding |
Publication series
Name | Proceedings - IEEE International Symposium on Circuits and Systems (ISCAS) |
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Volume | 4 |
ISSN (Print) | 0271-4310 |
Conference
Conference | 1993 IEEE International Symposium on Circuits and Systems (ISCAS) |
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Country/Territory | United States |
City | Chicago |
Period | 3/05/93 → 6/05/93 |
Internet address |
User-Defined Keywords
- Libraries
- Costs
- Integrated circuit interconnections
- Law
- Legal factors
- Adders
- Flow graphs
- Design automation