A graph partitioning problem for multiple-chip design

Yao-Ping Chen, Ting-Chi Wang, D.F. Wong

Research output: Chapter in book/report/conference proceedingConference proceedingpeer-review

3 Citations (Scopus)

Abstract

A new graph partitioning problem is introduced. It stems from a multiple-chip design style in which there is a chip library of chips containing predesigned circuit components (e.g., adders, multipliers, etc.) which are frequently used. Given an arbitrary circuit data flow graph, it is necessary to realize the circuit by appropriately choosing a set of chips from the chip library. In selecting chips from the chip library to realize a given circuit, both the number of chips used and the interconnection cost are to be minimized. The authors' new graph partitioning problem models this chip selection problem. An efficient solution to this problem is presented.
Original languageEnglish
Title of host publication1993 IEEE International Symposium on Circuits and Systems (ISCAS)
PublisherIEEE
Pages1778-1781
Number of pages4
ISBN (Print)0780312813
DOIs
Publication statusPublished - 6 May 1993
Event1993 IEEE International Symposium on Circuits and Systems (ISCAS) - Chicago, United States
Duration: 3 May 19936 May 1993
https://ieeexplore.ieee.org/xpl/conhome/1067/proceeding

Publication series

NameProceedings - IEEE International Symposium on Circuits and Systems (ISCAS)
Volume4
ISSN (Print)0271-4310

Conference

Conference1993 IEEE International Symposium on Circuits and Systems (ISCAS)
Country/TerritoryUnited States
CityChicago
Period3/05/936/05/93
Internet address

User-Defined Keywords

  • Libraries
  • Costs
  • Integrated circuit interconnections
  • Law
  • Legal factors
  • Adders
  • Flow graphs
  • Design automation

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