A fast simultaneous input vector generation and gate replacement algorithm for leakage power reduction

Keyphrases

• Benchmark Circuits 33%
• CMOS Gate 33%
• Combinational Circuits 33%
• Effective Method 33%
• Fast Heuristic 33%
• Gate Replacement 100%
• Heuristic Algorithms 33%
• Input Vector 100%
• Input Vector Control 33%
• Leakage Current 66%
• Leakage Current Reduction 33%
• Leakage Power Reduction 100%
• Low Leakage 33%
• Order of Magnitude 33%
• Replacement Algorithm 100%
• Replacement Method 33%
• Sleep Mode 33%
• Vector Control 33%
• Vector Signal Generation 100%

Computer Science

• And Gate 100%
• And-States 33%
• Benchmark Circuit 33%
• Combinational Circuit 33%
• Effective Method 33%
• Heuristic Algorithm 33%
• Leakage Current 100%
• Logic Gate 33%

Engineering

• Combinatorial Circuits 25%
• Input State 25%
• Input Vector 100%
• Logic Gate 25%
• Sleep Mode 25%