A distributed timing analysis framework for large designs

Tsung-Wei Huang; Martin D. F. Wong; Debjit Sinha; Kerim Kalafala; Natesan Venkateswaran

doi:10.1145/2897937.2897959

A distributed timing analysis framework for large designs

Tsung-Wei Huang, Martin D. F. Wong, Debjit Sinha, Kerim Kalafala, Natesan Venkateswaran

Office of the Provost

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

12 Citations (Scopus)

Abstract

Given ever-increasing circuit complexities, recent trends are driving the requirement for distributed timing analysis (DTA) in electronic design automation (EDA) tools. However, DTA has received little research attention so far and remains a critical problem. In this paper, we introduce a DTA framework for large designs. Our framework supports (1) general design partitions in distributed file systems, (2) non-blocking IO with event-driven loop for effective communication and computation overlap, and (3) an efficient messaging interface between application and network layers. The effectiveness and scalability of our framework has been evaluated on large hierarchical industry designs over a cluster with hundreds of machines.

Original language	English
Title of host publication	53rd ACM/IEEE Design Automation Conference
Publisher	Association for Computing Machinery (ACM)
Pages	1-6
Number of pages	6
ISBN (Electronic)	9781450342360, 9781467387293
ISBN (Print)	9781467387309
DOIs	https://doi.org/10.1145/2897937.2897959
Publication status	Published - Jun 2016
Event	53nd ACM/EDAC/IEEE Design Automation Conference, DAC 2016 - Austin, United States Duration: 5 Jun 2016 → 9 Jun 2016 https://dl.acm.org/doi/proceedings/10.1145/2897937 (Link to conference proceedings) https://ieeexplore.ieee.org/xpl/conhome/7502236/proceeding

Publication series

Name	Proceedings of ACM/IEEE Design Automation Conference
ISSN (Print)	0738-100X

Conference

Conference	53nd ACM/EDAC/IEEE Design Automation Conference, DAC 2016
Country/Territory	United States
City	Austin
Period	5/06/16 → 9/06/16
Internet address	https://dl.acm.org/doi/proceedings/10.1145/2897937 (Link to conference proceedings) https://ieeexplore.ieee.org/xpl/conhome/7502236/proceeding

Access to Document

10.1145/2897937.2897959

Cite this

@inproceedings{9b2dfa2c5b5c4b849e2f4501f355a600,

title = "A distributed timing analysis framework for large designs",

abstract = "Given ever-increasing circuit complexities, recent trends are driving the requirement for distributed timing analysis (DTA) in electronic design automation (EDA) tools. However, DTA has received little research attention so far and remains a critical problem. In this paper, we introduce a DTA framework for large designs. Our framework supports (1) general design partitions in distributed file systems, (2) non-blocking IO with event-driven loop for effective communication and computation overlap, and (3) an efficient messaging interface between application and network layers. The effectiveness and scalability of our framework has been evaluated on large hierarchical industry designs over a cluster with hundreds of machines.",

author = "Tsung-Wei Huang and Wong, {Martin D. F.} and Debjit Sinha and Kerim Kalafala and Natesan Venkateswaran",

note = "Publisher Copyright: {\textcopyright} 2016 by the Association for Computing Machinery; 53nd ACM/EDAC/IEEE Design Automation Conference, DAC 2016 ; Conference date: 05-06-2016 Through 09-06-2016",

year = "2016",

month = jun,

doi = "10.1145/2897937.2897959",

language = "English",

isbn = "9781467387309",

series = "Proceedings of ACM/IEEE Design Automation Conference",

publisher = "Association for Computing Machinery (ACM)",

pages = "1--6",

booktitle = "53rd ACM/IEEE Design Automation Conference",

address = "United States",

url = "https://dl.acm.org/doi/proceedings/10.1145/2897937, https://ieeexplore.ieee.org/xpl/conhome/7502236/proceeding",

}

Huang, T-W, Wong, MDF, Sinha, D, Kalafala, K & Venkateswaran, N 2016, A distributed timing analysis framework for large designs. in 53rd ACM/IEEE Design Automation Conference., 7544358, Proceedings of ACM/IEEE Design Automation Conference, Association for Computing Machinery (ACM), pp. 1-6, 53nd ACM/EDAC/IEEE Design Automation Conference, DAC 2016, Austin, Texas, United States, 5/06/16. https://doi.org/10.1145/2897937.2897959

A distributed timing analysis framework for large designs. / Huang, Tsung-Wei; Wong, Martin D. F.; Sinha, Debjit et al.
53rd ACM/IEEE Design Automation Conference. Association for Computing Machinery (ACM), 2016. p. 1-6 7544358 (Proceedings of ACM/IEEE Design Automation Conference).

Research output: Chapter in book/report/conference proceeding › Conference proceeding › peer-review

TY - GEN

T1 - A distributed timing analysis framework for large designs

AU - Huang, Tsung-Wei

AU - Wong, Martin D. F.

AU - Sinha, Debjit

AU - Kalafala, Kerim

AU - Venkateswaran, Natesan

PY - 2016/6

Y1 - 2016/6

N2 - Given ever-increasing circuit complexities, recent trends are driving the requirement for distributed timing analysis (DTA) in electronic design automation (EDA) tools. However, DTA has received little research attention so far and remains a critical problem. In this paper, we introduce a DTA framework for large designs. Our framework supports (1) general design partitions in distributed file systems, (2) non-blocking IO with event-driven loop for effective communication and computation overlap, and (3) an efficient messaging interface between application and network layers. The effectiveness and scalability of our framework has been evaluated on large hierarchical industry designs over a cluster with hundreds of machines.

AB - Given ever-increasing circuit complexities, recent trends are driving the requirement for distributed timing analysis (DTA) in electronic design automation (EDA) tools. However, DTA has received little research attention so far and remains a critical problem. In this paper, we introduce a DTA framework for large designs. Our framework supports (1) general design partitions in distributed file systems, (2) non-blocking IO with event-driven loop for effective communication and computation overlap, and (3) an efficient messaging interface between application and network layers. The effectiveness and scalability of our framework has been evaluated on large hierarchical industry designs over a cluster with hundreds of machines.

UR - https://dl.acm.org/doi/10.1145/2897937.2897959

UR - https://ieeexplore.ieee.org/document/7544358

UR - https://www.scopus.com/record/display.uri?eid=2-s2.0-84977143039&origin=inward

U2 - 10.1145/2897937.2897959

DO - 10.1145/2897937.2897959

M3 - Conference proceeding

SN - 9781467387309

T3 - Proceedings of ACM/IEEE Design Automation Conference

SP - 1

EP - 6

BT - 53rd ACM/IEEE Design Automation Conference

PB - Association for Computing Machinery (ACM)

T2 - 53nd ACM/EDAC/IEEE Design Automation Conference, DAC 2016

Y2 - 5 June 2016 through 9 June 2016

ER -

A distributed timing analysis framework for large designs

Abstract

Publication series

Conference

Access to Document

Other files and links

Fingerprint

Cite this