A channel/switchbox definition algorithm for building-block layout

Yang Cai, D. F. Wong

Research output: Chapter in book/report/conference proceedingConference proceedingpeer-review

5 Citations (Scopus)

Abstract

In this paper we study the problem of routing region definition in the VLSI building-block layout design style. We present an algorithm to decompose the routing area into a set of straight channels and switchboxes such that the number of switchboxes in the decomposition is minimized. Our algorithm is based on a graph-theoretic approach that makes use of an efficient polynomial time optimal algorithm for computing minimum clique covers of triangulated graphs. Experimental results indicate our algorithm performs well. We compared our algorithm with a previously known greedy approach and an exhaustive search optimal algorithm. For all the test problems we considered, our algorithm consistently outperformed the greedy algorithm, and it produced optimal solutions in almost all cases.

Original languageEnglish
Title of host publication27th ACM/IEEE Design Automation Conference - Proceedings 1990
PublisherAssociation for Computing Machinery (ACM)
Pages638-641
Number of pages4
ISBN (Print)081869650X, 9780897913638, 0897913639
DOIs
Publication statusPublished - Jan 1991
Event27th ACM/IEEE Design Automation Conference, DAC 1990 - Orlando, United States
Duration: 24 Jun 199027 Jun 1990
https://dl.acm.org/doi/proceedings/10.1145/123186
https://ieeexplore.ieee.org/xpl/conhome/790/proceeding

Publication series

NameACM/IEEE Design Automation Conference - Proceedings
ISSN (Print)0738-100X

Conference

Conference27th ACM/IEEE Design Automation Conference, DAC 1990
Country/TerritoryUnited States
CityOrlando
Period24/06/9027/06/90
Internet address

Scopus Subject Areas

  • Engineering(all)

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