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Keyphrases
3D IC
7%
Approximation Algorithms
5%
Area Optimization
8%
Assignment Problem
6%
Block Layout
7%
Board Level
8%
Buffer Insertion
20%
Buffer Sizing
6%
Bus Routing
7%
Channel Density
8%
Channel Routing
22%
Circuit Design
5%
Circuit Partitioning
13%
Circuit Performance
8%
Clock Tree
9%
Compaction
7%
Coupling Capacitance
10%
Deep Submicron
10%
Delay Minimization
10%
Delay Model
7%
Design Cost
6%
Design Rules
6%
Detailed Routing
7%
Directed Self-assembly
10%
Double Patterning Lithography
8%
Downscaling
5%
Dynamic Power
6%
Elmore Delay
7%
Elmore Delay Model
13%
Escape Routing
21%
Exact Algorithm
13%
Fast Algorithm
8%
Field Programmable Gate Arrays
13%
Floor Plan Design
16%
Floorplanning
44%
Flow-based
8%
FPGA-based
7%
Global Routing
15%
GPU Acceleration
9%
High Performance
15%
Lagrangian Relaxation
13%
Layer Assignment
10%
Layout Decomposition
6%
Layout Design
6%
Linear Time
7%
Lithography
10%
Logic Emulation
7%
Logic Module
10%
Low Power
9%
Manufacturability
8%
Mask Optimization
8%
Maze Routing
14%
Min-cut
6%
Netlist
6%
Network Flow
11%
Optical Proximity Correction
12%
Optimal Algorithm
23%
Optimization Problem
6%
Path-based
7%
PCB Routing
5%
Performance Optimization
6%
Physical Design
5%
Pin Assignment
13%
Polynomial Time
23%
Polynomial-time Algorithm
7%
Power Grid
10%
Rectangle
5%
Routability
13%
Router
27%
Routing Algorithm
24%
Routing Area
5%
Routing Problem
24%
Routing Resources
7%
Routing Solution
19%
Routing Tree
6%
Segmentation Design
5%
Self-aligned Double Patterning
10%
Sequence Pair
6%
Shortest Path Problem
6%
Simulated Annealing
12%
Slicing Floorplan
13%
Switch Module
9%
Technology Mapping
11%
Technology Node
7%
Time Constraints
11%
Time-optimal Algorithm
10%
Timer
6%
Timing Analysis
16%
Timing-driven
9%
Tree-based
6%
Triple Patterning
5%
Triple Patterning Lithography
9%
Two-layer
9%
VLSI Circuits
5%
VLSI Design
7%
Voltage Islands
8%
Wire Segments
9%
Wire Sizing
25%
Wirelength
17%
Wiring
6%
Computer Science
And Gate
5%
Assignment Problem
9%
Benchmark Circuit
7%
Buffer Insertion
20%
Building-Blocks
12%
Channel Density
6%
Clock Frequency
5%
Computer Aided Design
5%
Coupling Capacitance
9%
Data Structure
6%
Delay Minimization
9%
Design Problem
5%
Dynamic Power
8%
Dynamic Programming
5%
Efficient Algorithm
7%
Efficient Implementation
5%
Electronic Design Automation
5%
Elmore Delay Model
8%
Emulation
7%
Exact Algorithm
14%
Experimental Result
100%
Fast Algorithm
11%
Field Programmable Gate Array
72%
Floorplan Area
10%
Floorplan Design
16%
Floorplanning
27%
Global Placement
5%
Global Routing
18%
Graphics Processing Unit
25%
Integrated Circuit
13%
Lagrangian Relaxation
16%
Learning System
10%
Machine Learning
11%
Mapping Algorithm
6%
Minimization Problem
5%
Neural Network
5%
Open Source
7%
Optimal Algorithm
37%
Optimization Problem
9%
Performance Requirement
6%
Physical Design
8%
Pin Assignment
9%
Placement Algorithm
6%
Polynomial Time
24%
Polynomial Time Algorithm
7%
Power Consumption
5%
Printed Circuit Board
6%
Process Variation
8%
Product Design
5%
Routing Algorithm
31%
Routing Channel
14%
Routing Problem
46%
Routing Region
6%
Routing Resource
9%
Routing Solution
25%
Shortest Path Problem
10%
Signal Integrity
5%
Simulated Annealing
14%
Slicing Floorplan
16%
Solution Quality
7%
Speed-up
14%
Supply Voltage
5%
Table Lookup
5%
Technology Mapping
11%
Time Complexity
5%
Timing Analysis
22%
Timing Constraint
6%
Total Wirelength
6%
Tree Construction
6%
Engineering
Building Block
5%
Channel Layer
7%
Circuit Performance
6%
Constraint Length
5%
Coupling Capacitance
8%
Crosstalk
10%
Design Flow
6%
Design Rule
9%
Electric Power Utilization
6%
Exact Algorithm
11%
Experimental Result
44%
Extreme ultraviolet lithography
6%
Fast Algorithm
7%
Field Programmable Gate Array
18%
Graphics Processing Unit
5%
Integrated Circuit
6%
Interconnects
14%
Lagrangian Relaxation
6%
Linear Programming
6%
Linear Time
8%
Lithography
40%
Manufacturability
10%
Nodes
21%
Pin Assignment
10%
Polynomial Time
21%
Power Grid
6%
Routing Algorithm
11%
Routing Problem
19%
Routing Solution
12%
Supply Voltage
5%