Keyphrases
3D IC
6%
Approximation Algorithms
6%
Area Optimization
9%
Array-based
6%
Assignment Problem
6%
Block Layout
7%
Board Level
8%
Buffer Insertion
21%
Buffer Sizing
6%
Bus Routing
7%
Channel Density
8%
Channel Routing
23%
Circuit Partitioning
13%
Circuit Performance
9%
Clock Tree
8%
Compaction
7%
Congestion
5%
Coupling Capacitance
10%
Deep Submicron
11%
Delay Minimization
10%
Delay Model
7%
Design Cost
6%
Design Rules
7%
Detailed Routing
6%
Directed Self-assembly
11%
Double Patterning Lithography
9%
Downscaling
5%
Dynamic Power
6%
Elmore Delay
7%
Elmore Delay Model
13%
Escape Routing
22%
Exact Algorithm
14%
Fast Algorithm
9%
Field Programmable Gate Arrays
14%
Floor Plan Design
17%
Floorplanning
46%
Flow-based
9%
FPGA-based
7%
Global Routing
15%
GPU Acceleration
8%
High Performance
16%
Lagrangian Relaxation
13%
Layer Assignment
10%
Layout Decomposition
6%
Layout Design
6%
Linear Time
7%
Lithography
11%
Logic Emulation
8%
Logic Module
11%
Low Power
9%
Manufacturability
8%
Mask Optimization
6%
Maze Routing
15%
Min-cut
7%
Netlist
6%
Network Flow
12%
Optical Proximity Correction
9%
Optimal Algorithm
25%
Optimization Problem
6%
Path-based
7%
PCB Routing
6%
Performance Optimization
6%
Physical Design
6%
Pin Assignment
13%
Polynomial Time
24%
Polynomial-time Algorithm
7%
Power Grid
10%
Rectangle
6%
Routability
14%
Router
27%
Routing Algorithm
25%
Routing Area
6%
Routing Problem
25%
Routing Resources
7%
Routing Solution
20%
Routing Tree
6%
Segmentation Design
6%
Self-aligned Double Patterning
11%
Sequence Pair
6%
Shortest Path Problem
6%
Simulated Annealing
13%
Slicing Floorplan
14%
Switch Module
9%
Technology Mapping
11%
Technology Node
7%
Time Constraints
12%
Time-optimal Algorithm
10%
Timing Analysis
17%
Timing-driven
9%
Tree-based
6%
Triple Patterning
6%
Triple Patterning Lithography
9%
Two-layer
10%
VLSI Circuits
6%
VLSI Design
7%
Voltage Islands
9%
Wire Segments
9%
Wire Sizing
27%
Wirelength
16%
Wiring
6%
Computer Science
And Gate
5%
Assignment Problem
9%
Benchmark Circuit
8%
Buffer Insertion
21%
Building-Blocks
13%
Channel Density
6%
Clock Frequency
6%
Computer Aided Design
5%
Coupling Capacitance
9%
Data Structure
6%
Delay Minimization
10%
Design Problem
5%
Dynamic Power
8%
Dynamic Programming
5%
Efficient Algorithm
6%
Efficient Implementation
5%
Elmore Delay Model
8%
Exact Algorithm
14%
Experimental Result
100%
Fast Algorithm
12%
Field Programmable Gate Array
76%
Floorplan Area
10%
Floorplan Design
16%
Floorplanning
28%
Global Routing
17%
Graphics Processing Unit
25%
High Level Synthesis
5%
Integrated Circuit
12%
Lagrangian Relaxation
17%
Learning System
9%
Linear Programming
5%
Machine Learning
9%
Mapping Algorithm
6%
Minimization Problem
6%
Open Source
7%
Optimal Algorithm
39%
Optimization Problem
10%
Performance Requirement
6%
Physical Design
8%
Pin Assignment
10%
Placement Algorithm
6%
Polynomial Time
25%
Polynomial Time Algorithm
8%
Printed Circuit Board
7%
Process Variation
8%
Product Design
5%
Routing Algorithm
32%
Routing Channel
15%
Routing Problem
49%
Routing Region
6%
Routing Resource
10%
routing scheme
5%
Routing Solution
26%
Shortest Path Problem
11%
Signal Integrity
6%
Simulated Annealing
14%
Slicing Floorplan
17%
Solution Quality
8%
Speed-up
14%
Supply Voltage
5%
Table Lookup
6%
Technology Mapping
12%
Time Complexity
5%
Timing Analysis
23%
Timing Constraint
7%
Total Wirelength
6%
Transmission Line Model
5%
Tree Construction
5%
Very Large Scale Integration
5%
Engineering
Building Block
5%
Channel Layer
7%
Circuit Performance
6%
Constraint Length
5%
Coupling Capacitance
8%
Critical Cell
5%
Crosstalk
10%
Design Flow
6%
Design Power
5%
Design Rule
9%
Electric Power Utilization
6%
Exact Algorithm
12%
Experimental Result
45%
Extreme-Ultraviolet Lithography
7%
Fast Algorithm
7%
Field Programmable Gate Array
19%
Graphics Processing Unit
5%
Integrated Circuit
6%
Interconnects
14%
Lagrangian Relaxation
7%
Linear Programming
8%
Linear Time
8%
Lithography
41%
Manufacturability
10%
Max
5%
Metal Layer
5%
Nodes
23%
Pin Assignment
10%
Polynomial Time
22%
Power Grid
7%
Routing Algorithm
11%
Routing Problem
19%
Routing Solution
13%
Supply Voltage
5%