Keyphrases
Floorplanning
46%
Router
27%
Wire Sizing
27%
Routing Algorithm
25%
Optimal Algorithm
25%
Routing Problem
25%
Polynomial Time
24%
Channel Routing
23%
Escape Routing
22%
Buffer Insertion
21%
Routing Solution
20%
Floor Plan Design
17%
Timing Analysis
17%
Wirelength
16%
High Performance
16%
Global Routing
15%
Maze Routing
15%
Field Programmable Gate Arrays
14%
Exact Algorithm
14%
Slicing Floorplan
14%
Routability
14%
Lagrangian Relaxation
13%
Circuit Partitioning
13%
Pin Assignment
13%
Elmore Delay Model
13%
Simulated Annealing
13%
Network Flow
12%
Time Constraints
12%
Technology Mapping
11%
Deep Submicron
11%
Directed Self-assembly
11%
Self-aligned Double Patterning
11%
Logic Module
11%
Lithography
11%
Layer Assignment
10%
Delay Minimization
10%
Coupling Capacitance
10%
Power Grid
10%
Time-optimal Algorithm
10%
Two-layer
10%
Triple Patterning Lithography
9%
Low Power
9%
Optical Proximity Correction
9%
Wire Segments
9%
Switch Module
9%
Timing-driven
9%
Fast Algorithm
9%
Double Patterning Lithography
9%
Area Optimization
9%
Voltage Islands
9%
Circuit Performance
9%
Flow-based
9%
Manufacturability
8%
Channel Density
8%
Clock Tree
8%
GPU Acceleration
8%
Board Level
8%
Logic Emulation
8%
Polynomial-time Algorithm
7%
Technology Node
7%
FPGA-based
7%
Routing Resources
7%
Bus Routing
7%
VLSI Design
7%
Linear Time
7%
Path-based
7%
Block Layout
7%
Compaction
7%
Elmore Delay
7%
Delay Model
7%
Design Rules
7%
Min-cut
7%
Performance Optimization
6%
Layout Decomposition
6%
Tree-based
6%
Buffer Sizing
6%
Design Cost
6%
Netlist
6%
Routing Tree
6%
Detailed Routing
6%
Dynamic Power
6%
Layout Design
6%
Optimization Problem
6%
Shortest Path Problem
6%
Sequence Pair
6%
VLSI Circuits
6%
Assignment Problem
6%
Mask Optimization
6%
Wiring
6%
Rectangle
6%
Routing Area
6%
Approximation Algorithms
6%
Physical Design
6%
3D IC
6%
PCB Routing
6%
Segmentation Design
6%
Triple Patterning
6%
Array-based
6%
Congestion
5%
Downscaling
5%
Computer Science
Experimental Result
100%
Field Programmable Gate Array
76%
Routing Problem
49%
Optimal Algorithm
39%
Routing Algorithm
32%
Floorplanning
28%
Routing Solution
26%
Graphics Processing Unit
25%
Polynomial Time
25%
Timing Analysis
23%
Buffer Insertion
21%
Global Routing
17%
Lagrangian Relaxation
17%
Slicing Floorplan
17%
Floorplan Design
16%
Routing Channel
15%
Speed-up
14%
Exact Algorithm
14%
Simulated Annealing
14%
Building-Blocks
13%
Integrated Circuit
12%
Technology Mapping
12%
Fast Algorithm
12%
Shortest Path Problem
11%
Floorplan Area
10%
Routing Resource
10%
Delay Minimization
10%
Pin Assignment
10%
Optimization Problem
10%
Coupling Capacitance
9%
Assignment Problem
9%
Machine Learning
9%
Learning System
9%
Dynamic Power
8%
Elmore Delay Model
8%
Process Variation
8%
Physical Design
8%
Benchmark Circuit
8%
Solution Quality
8%
Polynomial Time Algorithm
8%
Open Source
7%
Printed Circuit Board
7%
Timing Constraint
7%
Efficient Algorithm
6%
Channel Density
6%
Mapping Algorithm
6%
Data Structure
6%
Placement Algorithm
6%
Performance Requirement
6%
Routing Region
6%
Minimization Problem
6%
Clock Frequency
6%
Total Wirelength
6%
Signal Integrity
6%
Table Lookup
6%
Time Complexity
5%
Efficient Implementation
5%
And Gate
5%
Supply Voltage
5%
Dynamic Programming
5%
Tree Construction
5%
Computer Aided Design
5%
Product Design
5%
Design Problem
5%
Very Large Scale Integration
5%
High Level Synthesis
5%
Linear Programming
5%
Transmission Line Model
5%
routing scheme
5%
Engineering
Experimental Result
45%
Lithography
41%
Nodes
23%
Polynomial Time
22%
Field Programmable Gate Array
19%
Routing Problem
19%
Interconnects
14%
Routing Solution
13%
Exact Algorithm
12%
Routing Algorithm
11%
Manufacturability
10%
Pin Assignment
10%
Crosstalk
10%
Design Rule
9%
Coupling Capacitance
8%
Linear Time
8%
Linear Programming
8%
Fast Algorithm
7%
Channel Layer
7%
Lagrangian Relaxation
7%
Extreme-Ultraviolet Lithography
7%
Power Grid
7%
Electric Power Utilization
6%
Design Flow
6%
Circuit Performance
6%
Integrated Circuit
6%
Building Block
5%
Supply Voltage
5%
Constraint Length
5%
Graphics Processing Unit
5%
Metal Layer
5%
Design Power
5%
Critical Cell
5%
Max
5%